Low Power Digital Design Using Asynchronous Fine Grain Logic

In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. Pipeline stage in the AFPL circuit is consisting of positive feedback adiabatic logic (PFAL) gates that implement the logic function of the stage, and a handshake controller, that handles handshaking with the neighboring stages and gives power to the PFAL gates. The partial charge reuse (PCR) mechanism can be added in the AFPL circuit. Using the PCR mechanism, part of the charge on the output nodes of a PFAL gate entering the discharge phase can be used to charge the output nodes of another PFAL gate which is more enough to complete evaluate phase, reducing the energy dissipation. AFPLPCR adopts an enhanced C-element, called C∗-element, in its handshake controllers such that an PFAL gate in AFPL-PCR can enter into the sleep mode earlier once the output has been received by the downstream pipeline stage. The proposed power gating technique is implemented with minimal control overheads and the interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries. Keywords— Asynchronous Circuits, Logic Gates, Low-Power Electronics, Power Gating, Partial Charge Reuse.